This application claims priority to Korean Application No. 2001-2376, filed Jan. 16, 2001, the disclosure of which is hereby incorporated herein by reference.
Synchronous memory devices have been recently developed in order to realize high speed operation. In a typical synchronous memory device, command signals are input in synchronization with an external clock (a xe2x80x9csystem clockxe2x80x9d), and output data is produced in synchronization with edges of the system clock. In a typical synchronous memory device, data stored in a memory cell array is typically read in synchronization with an internal clock generated by an internal clock generator. The read data is typically output using an output control clock generated by a delay locked loop circuit. In particular, the internal clock generator typically generates the internal clock responsive to the system clock, and the delay locked loop circuit typically generates the output control clock in response to the system clock.
A typical synchronous memory device includes a latency control circuit that generates a latency control signal that controls latency, i.e., a delay between reading of data and appearance of the data at the output of an output buffer. The output buffer typically outputs data read from a memory cell array in response to an output control signal generated responsive to the latency control signal. In some conventional memory devices, latency can be correctly controlled only when timing between the read data that is synchronized with the internal clock and the output control clock is correctly controlled. For example, a column address strobe (CAS) latency means the number of clock cycles of a system clock from the time at which an external read command signal is applied to the time at which valid data is output from the synchronous memory device.
FIG. 1 is a circuit diagram showing a latency control circuit of a conventional synchronous semiconductor memory device, while FIG. 2 is a timing diagram showing a conventional latency control technique for the conventional synchronous memory device shown in FIG. 1, in particular, a technique that provides a CAS latency of 5 and a burst length (BL) of 4. Referring to FIG. 1, the conventional latency control circuit includes a portion 11 for generating a read status signal COSR and a portion 13 for generating the latency control signal LATENCY by delaying the read status signal COSR. The portion 11 is controlled by an internal clock PCLK generated by an internal clock generator of the synchronous memory device. The read status signal COSR is asserted to a logic xe2x80x9chighxe2x80x9d level when an external read command signal Ext-Read CMD is applied and is asserted to a logic xe2x80x9clowxe2x80x9d level in response to assertion of at least one of an internal burst end signal Int-Burst-End, a burst stop command signal Ext-burst-Stop CMD or a read interrupt precharge command signal Ext-RIP CMD. The portion 13 is controlled by an output control clock CLKDQ generated by a delay locked loop circuit. The portion 13 samples the read status signal COSR and transfers data through a series of flip-flops under control of the output control clock CLKDQ.
As shown, for a CAS latency of 5, the portion 13 delays the read status signal COSR by four clock cycles of the output control clock CLKDQ. As shown in the timing diagram of FIG. 2, the internal clock PCLK lags the externally applied system clock CLK by a predetermined time t1, while the output control clock CLKDQ leads the system clock CLK by a predetermined time t2. Though not shown in the timing diagram of FIG. 2, when a read command signal Ext-Read CMD is asserted during a cycle of the system clock CLK, the read status signal COSR is asserted to a logic xe2x80x9chighxe2x80x9d level after a predetermined delay following assertion of the read command signal Ext-Read CMD, due to the delay of the internal paths of the portion 11. Also, as shown in the timing diagram of FIG. 2, when the read interrupt precharge command signal Ext-RIP is asserted after three cycles (i.e., around a time T) of the system clock CLK following assertion of the read command signal Ext-Read CMD, the read status signal COSR is asserted to a logic xe2x80x9clowxe2x80x9d following a delay time t3 from time T due to the delay of the internal paths of the portion 11. The read status signal COSR is sampled in the portion 13 responsive to next rising edge of the output control clock CLKDQ.
When the sum of the times t3 and t2 exceeds the period tCC of the system clock CLK, the read status signal COSR may not be correctly sampled by the portion 13, which may result in incorrect latency control that causes output data DOUT to be produced one clock cycle later than desired. Thus, for example, in the conventional latency control circuit operations illustrated, the period tCC of the system clock CLK should be constrained to be greater than the sum of times t3 and t2 to provide desired operation (e.g., if t3 is 3 nanoseconds (ns) and t2 is 3 ns, tCC should be greater than 6 ns). Limitations of the latency control circuit can thus constrain the system clock CLK period (and limit the clock frequency), even though other portions of the memory device may be capable of operating at faster clock speeds. This can limit the overall performance of the synchronous memory device.
According to some embodiments of the present invention, a synchronous memory device includes a first clock generator circuit that receives a first clock signal and generates a second clock signal therefrom, the second clock signal lagging the first clock signal by a first predetermined time. The memory device also includes a second clock generator circuit that receives the first clock signal and generates a third clock signal therefrom, the third clock signal leading the first clock signal by a second predetermined time. A synchronous read status signal generator circuit is coupled to the first clock generator circuit and receives a read initiation signal indicative of initiation of a read operation and a read termination signal indicative of termination of the read operation. The synchronous read status signal generator circuit produces a transition in a read status signal in response to assertion of either of the read initiation signal or the read termination signal, and latches the read status signal responsive to the second clock signal to generate a synchronized read status signal. A latency signal generator circuit is coupled to the second clock generator circuit and to the synchronous read status signal generator circuit, receives the synchronized read status signal, and generates a latency control signal therefrom responsive to the third clock signal. The memory device further includes a memory cell array and a data output buffer coupled to the memory cell array that receives data from the memory cell array and outputs the received data responsive to an output control signal. An output control circuit generates the output control signal responsive to the latency control signal.
In some embodiments of the present invention, the synchronous read status signal generator circuit transitions the synchronized read status signal upon a next-occurring edge of the second clock signal after transition of the read status signal. The synchronous read status signal generator circuit may, in response to transition of the read status signal during a first cycle of the first clock signal, transition the synchronized read status signal during a second cycle of the first clock signal. The first cycle of the first clock signal may immediately precede the second cycle of the first clock signal.
In some embodiments of the present invention, the synchronous read status signal generator circuit comprises a read status signal generator circuit that receives the read initiation signal and the read termination signal and responsively generates the read status signal and a synchronous delay circuit, e.g., an edge-triggered flip-flop, that generates the synchronized read status signal from the read status circuit responsive to the second clock signal. The latency signal generator circuit may include a level-triggered latch that receives the synchronized read status signal and that latches the received synchronized read status signal responsive to a level of the third clock signal.
Related operating methods for memory devices are also provided.